Gate-last process is an approach to fabricate metal gate structures, which is characterized by forming a metal gate after performing ion implantation and high-temperature annealing to source/drain regions. The gate-first process is another approach, which is characterized by forming a metal gate before performing ion implantation and high-temperature annealing to source/drain regions.
Compared with the gate-first process, since the gate-last process protects the metal gate from the high-temperature annealing process, which is usually implanted at a temperature over 1000° C., it has the advantages of lower material requirement for the metal gate and higher process integration. Therefore, the gate-late process has been widely applied in the semiconductor technology.
The conventional gate-late process comprises the following steps:
Step 1: referring to FIG. 1, a semiconductor substrate 1 is provided. A dummy gate dielectric layer 4 and a dummy gate electrode 3 are formed in sequence on a surface of the semiconductor substrate 1. Then, source/drain regions are formed in the semiconductor substrate 1 on opposing sides of the dummy gate electrode 3 and metal silicide 11 is formed in an upper portion of the source/drain regions. After that, sidewall spacers 2 are formed on opposing sides of the dummy gate electrode 3.
Step 2: referring to FIG. 1, an interlayer insulator layer 5, i.e., a silicon nitride layer, and an interlayer dielectric layer (IDL) 6, are successively deposited on a semiconductor structure formed after the Step 1. Referring to FIG. 2, a portion of the silicon nitride layer 5 and the interlayer dielectric layer 6 above the dummy gate electrode 3 and the sidewall spacers 2 are removed by chemical mechanical polishing.
Step 3: referring to FIG. 3 and FIG. 4, the dummy gate electrode 3 and the dummy gate dielectric layer 4 below the dummy gate electrode 3 are removed to expose the semiconductor substrate 1.
Step 4: referring to FIG. 5, a gate dielectric layer 7 and a metal gate 8 are formed on the surface of the semiconductor substrate 1 within the sidewall spacers 2.
In the above Step 3, after the removal of the dummy gate electrode 3, the dummy gate dielectric 4 is conventionally removed by wet etching, that is, using an acid solution to remove the dummy gate dielectric 4. However, in order to reduce manufacturing cost and subsequent overlay error, photoresist is not applied to the interlayer dielectric layer 6 outside the sidewall spacers 2. As a result, the interlayer dielectric layer 6 may be etched together with the dummy gate dielectric 4 as it also contains oxide like the dummy gate dielectric 4. Referring to FIG. 3, the dummy gate dielectric layer 4 is formed with high density due the high process temperature of approximately 1000° C. and less impurities exist on the surface of the semiconductor substrate 1 within the sidewall spacers 2. By contrast, the interlayer dielectric layer 6 outside the sidewall spacers 2 is formed with low density due to the lower process temperature of approximately 400° C. and more impurities in this region. When the acid solution etches the dummy gate dielectric layer 4 together with the interlayer dielectric layer 6, the etch rate of the interlayer dielectric layer 6 with low density is faster than that of the dummy gate dielectric layer 4 with high density, which results in a structure as illustrated in FIG. 6. Due to the high etch rate of the interlayer dielectric layer 6 outside the sidewall spacers 2, when the dummy gate dielectric layer 4 within the sidewall spacers 2 is removed, the height of the interlayer dielectric layer 6 is already lower than the height of the sidewall spacers 2, such semiconductor device cannot be treated with subsequent process steps and has to be scrapped.
To solve the problem above, a remote plasma of a mixing gas comprising NF3 and NH3 is used to remove the dummy gate dielectric layer 4. Since the etch rate of the dummy gate dielectric 4 and that of the interlayer dielectric layer 6 by the plasma of NF3/NH3 are the same, the height reduction rate of the dummy gate dielectric layer 4 within the sidewall spacers 2 and that of the interlayer dielectric layer 6 outside the sidewall spacers 2 keep consistent. However, after removing the dummy gate dielectric layer 4 and the interlayer dielectric layer 6, fluorine residue may remain on the surface of semiconductor device. Particularly, the fluorine residue on the surface of the semiconductor substrate 1 may cause offset of the inversion layer between the source/drain regions and increased gate current leakage, which affects the performance of the semiconductor device.
In view of the drawbacks mentioned above, there exists a need to develop a method to protect the semiconductor devices from the effect of the fluorine residue on the surface of the semiconductor substrate.